Wafer Cut and Rotation for Compound Yield Improvement in 3D Wafer-on-Wafer Stacking

Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, smaller chip area, etc. Wafer-on-wafer stacking is most attractive for 3D IC fabrication, but it suffers from low compound yield. To improve the compound yield, two efforts have been done in this work. First, a hybrid waferon-wafer stacking procedure is proposed which incorporates rotationally symmetric wafers and running repository based best-pair matching algorithm. Further, a novel manipulation of wafer cut and rotation (CR) is proposed. In this method, wafers with rotational symmetry are either cut to 4 or 2 sectors. These sectors are then rotated and used to replenish the repositories. The CR method is further combined with best-pair matching algorithm for compound yield evaluation. Simulation results show that for wafers with nine different defect distributions, plain rotation of wafers offers trivial benefits in yield, which suggests that the proposed hybrid stacking procedure is not as beneficial as what it is expected to be. Experiment results on CR method however shows significant higher yield than existing methods. The advantage becomes even more obvious with the increase of repository size and the number of stacked layers. For 3D IC with 7 layers, the relative yield increase of CR method over existing method can reach as high as 189%.